This invention relates to D.C. to D.C. converters, and more particularly, to a D.C. to D.C. converter having means to prevent simultaneous conduction of its power switching transistors.
A D.C. to D.C. voltage converter is normally used to convert a D.C. power input at one voltage level to a D.C. power output at a different voltage level. The D.C. isolation between the input and output power signals is normally provided by a saturable transformer. Power switching transistors are typically provided to sequentially drive a core of a saturable transformer into its positive and negative saturation conditions, thereby developing a square-wave time varying signal which is further rectified into a D.C. signal. The control circuit for the power switching transistor is typically arranged across a secondary or base winding of the transformer and operates upon the collapse of the inductive state of the transformer near the saturation conditions to sequentially turn-on and turn-off the conductive states of the transistors. Due to the high current switching of the power transistors it is desirable that the power transistors not be simultaneously conductive. This problem is addressed by A. I. Pressman, in a textbook published in 1977 by Hayden Book Company, Inc., Rochelle Park, N.J., entitled, "Switching and Linear Power Supply, Power Converter Design", in paragraph 8.7.1. Pressman describes two solutions to the simultaneous conduction of the power switching transistors, both related to the development of the turn-on signal for the transistors. The first solution uses an RC delay for developing the turn-on signal and the second solution uses monostable and logic gate delay for developing the turn-on signal. Either of these solutions requires knowledge of the storage time of the power transistor in order to determine the desired delay. Also the storage time of the power transistor is a function, in part, of load current and junction temperature both of which are variable quantities. It is considered desirable to automatically provide means for inhibiting simultaneous conduction that does not depend on variable quantities.
The simultaneous conduction of the power switching transistors is also described in U.S. Pat. No. 4,195,333 issued to K. K. Hedel on Mar. 25, 1980 and assigned to the same assignee of the present invention. In the U.S. Pat. No. 4,195,333 a synchronous circuit utilizing a two-phase oscillator provides clock signals which inhibit simultaneous conduction of the switching transistors. It is considered desirable to inhibit simultaneous conduction of the power switching without the need of a synchronous type of circuit.
Accordingly, it is an object of the present invention to provide a D.C. to D.C. converter not dependent on a variable quantity or requiring clocking signals to prevent simultaneous conduction of power switching transistors used to control the excitation of a saturable transformer.
It is a further object of the present invention to provide a D.C. to D.C. voltage converter which reduces the peak amplitude of the saturation current within the switching transistors.
It is a still further object of the present invention to inhibit simultaneous conduction of power transistors and thereby reduce power losses of the power transistors.
These and other objects of the invention will become apparent to those skilled in the art upon consideration of the following description of the invention.